1. Field of the Invention
This invention relates to connection structures, and, more particularly, to a connection structure in a semiconductor package.
2. Description of Related Art
In a flip-chip packaging process, a semiconductor element is disposed on and electrically connected to a package substrate via solder bumps, and the package substrate and the semiconductor element are packaged. Therefore, both the semiconductor element and the package substrate have connection pads disposed thereon for the package substrate to be electrically connected to the semiconductor element (chip) via the solder bumps.
As shown in FIG. 1, a substrate 30 (e.g., a package substrate or a semiconductor chip) has a plurality of aluminum connection pads 300 (only one of the connection pads 300 is shown here to represent all of the connection pads 300), and an insulation protection layer 31 made of polyimide is formed on the substrate 30 and exposes the connection pads 300. A patterning process is performed on an exposed surface of the connection pads 300, i.e., forming a metallic layer 11 composed of a titanium portion 11a, a copper portion 11b and a nickel portion 11c to act as an under bump metallurgy (UBM). Then, conductive bumps 12 are disposed on the nickel layer 11c, and a solder tin material 13 is formed on the conductive bumps 12 and reflowed to form solder bumps that act as a connection structure 1 that electrically connects the package substrate with the semiconductor chip.
In the connection structure 1, since the metallic layer 11 does not cover the entire exposed surface of the connection pads 300 and the titanium portion 11a in the metallic layer 11 is bonded to the polyimide (i.e., the insulation protection layer 31) securely, the titanium portion 11a cannot be removed completely from a surface of the insulation protection layer 31 when an excessive metal material is etched and removed (i.e., the patterning process), and a residual titanium metal stays on the insulation protection layer 31. As a result, an electrical leakage phenomenon occurs at the connection structure 1 when the chip is in operation after the package substrate is flip-chipped on and bonded to the chip, and the electrical function of the overall package is affected.
Since the metallic layer 11 does not cover the entire exposed surface of the connection pads 300, a colloid material is likely to flow to the surface of the connection pads 300 during the subsequent underfill step of a flip-chip process, and the colloid material is likely to be peeled off from the substrate 30. As a result, the connection structure 1 is cracked, and the reliability of an electronic product is affected.
In order to address the compact-size and low-profile requirements for an electronic product, the substrate 30 is designed to have small pitches. For example, a distance between any two of the conductive bumps 12 is limited to be equal to or less than 80 μm. Such a small pitch results in the electrical leakage phenomenon and the connection structure 1 is more likely to be cracked, which is contradictory to the miniature design.
Therefore, how to overcome the problems of the prior art is becoming an urgent issue in the art.